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Number systems, logic gates, K-maps, combinational and sequential circuit design.
| Base | System | Digits | Prefix | Example |
|---|---|---|---|---|
| 2 | Binary | 0, 1 | 0b | 0b1010 = 10 |
| 8 | Octal | 0–7 | 0o | 0o12 = 10 |
| 10 | Decimal | 0–9 | (none) | 10 |
| 16 | Hexadecimal | 0–9, A–F | 0x | 0xA = 10 |
┌─────────────────────────────────────────────────────────────────┐
│ NUMBER SYSTEM CONVERSIONS │
├─────────────────────────────────────────────────────────────────┤
│ │
│ BINARY → DECIMAL: │
│ 1 0 1 1 . 0 1 │
│ │ │ │ │ │ │ │
│ 8 4 2 1 . ½ ¼ → 8+0+2+1+0+¼ = 11.25 │
│ Positional: Σ bit_i × 2^i │
│ │
│ DECIMAL → BINARY (Successive Division): │
│ 25 ÷ 2 = 12 R 1 ↑ (LSB) │
│ 12 ÷ 2 = 6 R 0 │ │
│ 6 ÷ 2 = 3 R 0 │ Read remainders bottom → top │
│ 3 ÷ 2 = 1 R 1 │ 25₁₀ = 11001₂ │
│ 1 ÷ 2 = 0 R 1 ↑ (MSB) │
│ │
│ BINARY → OCTAL: Group in 3s from right │
│ 110 101 011 → 6 5 3 → 0653₈ │
│ │
│ BINARY → HEX: Group in 4s from right │
│ 1010 1111 0011 → A F 3 → 0xAF3 │
│ │
│ HEX → BINARY: Replace each hex digit with 4 bits │
│ 0xBEEF → 1011 1110 1110 1111 │
│ │
│ FRACTIONAL CONVERSION (Decimal to Binary): │
│ 0.625 × 2 = 1.25 → 1 ↑ (MSB of fraction) │
│ 0.25 × 2 = 0.5 → 0 │ │
│ 0.5 × 2 = 1.0 → 1 ↑ (LSB) → 0.625 = 0.101₂ │
└─────────────────────────────────────────────────────────────────┘BINARY ADDITION: BINARY SUBTRACTION:
0 + 0 = 0 0 - 0 = 0
0 + 1 = 1 1 - 0 = 1
1 + 0 = 1 1 - 1 = 0
1 + 1 = 10 (0 carry 1) 10 - 1 = 1 (borrow)
2'S COMPLEMENT SUBTRACTION:
A - B = A + (2's complement of B)
BCD (Binary-Coded Decimal):
Each decimal digit → 4 bits
9 → 1001, 5 → 0101, 95 → 1001 0101
Invalid codes: 1010–1111 (A-F)
BCD add: if sum > 9, add 0110 (6) correction| Code | Bits | Detects | Corrects | Overhead |
|---|---|---|---|---|
| Parity Bit | n+1 | 1-bit odd errors | No | 1 bit |
| Hamming Code | n + ⌈log₂(n+1)⌉ | 1-bit + some 2-bit | 1-bit | ≈ log₂(n) bits |
| CRC | n + r (polynomial) | Burst errors | No | r bits (deg of poly) |
| Repetition (3x) | 3n | 2-bit | 1-bit | 2n bits |
+6 correction rule: after adding two BCD digits, if the 4-bit result is > 9 (1001) or has a carry, add 0110 to correct. For Hamming codes, parity bits go at positions 1, 2, 4, 8, 16... (powers of 2).| Gate | Symbol | Expression | NAND Equivalent | NOR Equivalent |
|---|---|---|---|---|
| AND | A·B | Y = AB | (A↑A)↓(B↑B) | ((A↓B)↓(A↓B))↓((A↓B)↓(A↓B)) |
| OR | A+B | Y = A + B | ((A↑B)↑(A↑B)) | (A↓A)↓(B↓B) |
| NOT | Ā | Y = Ā | (A↑A) | (A↓A) |
| XOR | A⊕B | Y = A⊕B | ((A↑(A↑B))↑B) | — |
| XNOR | A⊙B | Y = A⊕B̄ | ((A↑A)↑(B↑B))↑((A↑B)↑(A↑B)) | — |
| NAND | (A·B)̄ | Y = (AB)' | — | — |
| NOR | (A+B)̄ | Y = (A+B)' | — | — |
┌─────────────────────────────────────────────────────────────────┐
│ BOOLEAN ALGEBRA — KEY LAWS │
├─────────────────────────────────────────────────────────────────┤
│ │
│ FUNDAMENTAL LAWS: │
│ Identity: A + 0 = A A · 1 = A │
│ Null Element: A + 1 = 1 A · 0 = 0 │
│ Idempotent: A + A = A A · A = A │
│ Complement: A + Ā = 1 A · Ā = 0 │
│ Involution: Ā̄ = A │
│ │
│ COMMUTATIVE: A + B = B + A A · B = B · A │
│ ASSOCIATIVE: (A+B)+C = A+(B+C) (AB)C = A(BC) │
│ DISTRIBUTIVE: A(B+C) = AB+AC (A+B)(A+C) = A+BC │
│ │
│ DEMORGAN'S THEOREM (MOST IMPORTANT): │
│ (A + B + C + ...)' = A' · B' · C' · ... │
│ (A · B · C · ...)' = A' + B' + C' + ... │
│ "Break the bar, change the sign" │
│ │
│ ABSORPTION: │
│ A + AB = A A(A + B) = A │
│ A + ĀB = A + B A + B = AB + Ā + B (consensus) │
│ │
│ CONSENSUS THEOREM: │
│ AB + ĀC + BC = AB + ĀC (BC is redundant) │
│ │
│ SIMPLIFICATION TRICKS: │
│ A⊕A = 0 | A⊕0 = A | A⊕1 = Ā | A⊕Ā = 1 │
│ A⊙A = 1 | A⊙0 = Ā | A⊙1 = A | A⊙Ā = 0 │
└─────────────────────────────────────────────────────────────────┘K-MAP PROCEDURE:
1. Plot 1s from truth table onto K-map grid
2. Group adjacent 1s in powers of 2: 1, 2, 4, 8, 16...
3. Groups must be rectangular (or square)
4. Groups can wrap around edges (toroidal)
5. Maximize group sizes (fewer terms)
6. Every 1 must be covered (can overlap)
7. Don't Cares (X): use if helpful, ignore otherwise
SIZES:
2-variable: 2×2 (4 cells)
3-variable: 2×4 (8 cells)
4-variable: 4×4 (16 cells)
5-variable: two 4×4 layers (32 cells)
ORDER: Gray code for axes: 00, 01, 11, 10
(only ONE bit changes between adjacent cells)| Operation | Using NAND Only | Using NOR Only |
|---|---|---|
| NOT | (A NAND A) | (A NOR A) |
| AND | ((A NAND A) NAND (B NAND B)) NAND ((A NAND A) NAND (B NAND B)) | ((A NOR B) NOR (A NOR B)) |
| OR | ((A NAND B) NAND (A NAND B)) | ((A NOR A) NOR (B NOR B)) |
| XOR | NAND implementation uses 4 NAND gates | NOR implementation uses 5 NOR gates |
Don't Cares (X) give you flexibility — include them in groups only if it simplifies the expression.| Type | Select Lines | Outputs | Formula |
|---|---|---|---|
| 2:1 MUX | 1 (S) | Y | Y = S̄·I₀ + S·I₁ |
| 4:1 MUX | 2 (S₁,S₀) | Y | Y = S̄₁S̄₀I₀ + S̄₁S₀I₁ + S₁S̄₀I₂ + S₁S₀I₃ |
| 8:1 MUX | 3 (S₂,S₁,S₀) | Y | Y = Σ mᵢ·Iᵢ for each select combo |
| 16:1 MUX | 4 | Y | Extends similarly; tree of smaller MUXes |
| Type | Input Lines | Outputs | Use |
|---|---|---|---|
| 1:2 DEMUX | 1 data + 1 select | 2 | Route data to one of 2 outputs |
| 1:4 DEMUX | 1 data + 2 select | 4 | Route data to one of 4 outputs |
| 2:4 Decoder | 2 input | 4 active outputs | One output HIGH per input combo |
| 3:8 Decoder | 3 input | 8 active outputs | Address decoding, memory select |
| BCD to 7-seg | 4 BCD input | 7 segment outputs | Display driver |
| Type | Inputs | Outputs | Behavior |
|---|---|---|---|
| Binary Encoder | 2ⁿ | n | One-hot input → binary output; only ONE input active |
| Octal-to-Binary | 8 | 3 | 8 lines → 3-bit binary; if D₅=1 → 101 |
| Priority Encoder | 2ⁿ | n + Valid | Highest priority input wins; GS (group signal) indicates any active |
| 8:3 Priority Encoder | 8 | 3 + GS + EO | D₇ highest; if D₇=1 → 111; cascading with EO/GS |
┌─────────────────────────────────────────────────────────────────┐
│ IMPORTANT COMBINATIONAL CIRCUITS │
├─────────────────────────────────────────────────────────────────┤
│ │
│ HALF ADDER: │
│ Sum = A ⊕ B │
│ Carry = A · B │
│ │
│ FULL ADDER (2 Half Adders + 1 OR): │
│ Sum = A ⊕ B ⊕ Cin │
│ Carry = A·B + Cin·(A ⊕ B) │
│ Delay: Sum = 2 XOR gates; Carry = 2 gate delays │
│ │
│ n-BIT RIPPLE CARRY ADDER: │
│ • n Full Adders cascaded │
│ • Carry ripples from LSB to MSB │
│ • Worst-case delay = 2n gate delays │
│ • Area efficient but slow for large n │
│ │
│ CARRY LOOK-AHEAD ADDER (CLA): │
│ Generate: Gᵢ = Aᵢ · Bᵢ │
│ Propagate: Pᵢ = Aᵢ ⊕ Bᵢ │
│ C₁ = G₀ + P₀·C₀ │
│ C₂ = G₁ + P₁·G₀ + P₁·P₀·C₀ │
│ C₃ = G₂ + P₂·G₁ + P₂·P₁·G₀ + P₂·P₁·P₀·C₀ │
│ Carry computed in parallel → O(log n) delay │
│ Trade-off: More hardware for speed │
│ │
│ COMPARATOR: │
│ A = B: XOR all bits, NOR them │
│ A > B: (A₃B̄₃) + (A₃⊙B₃)(A₂B̄₂) + ... │
│ A < B: (Ā₃B₃) + (A₃⊙B₃)(Ā₂B₂) + ... │
│ 4-bit IC: 7485 (cascadable with cascading inputs) │
│ │
│ PARITY GENERATOR/CHECKER: │
│ Even parity: XOR all data bits │
│ For n bits: P = D₀ ⊕ D₁ ⊕ D₂ ⊕ ... ⊕ Dₙ₋₁ │
│ Checker: XOR all received bits including parity → 0 = OK │
└─────────────────────────────────────────────────────────────────┘Carry Look-Ahead Addersare essential in ALU design — ripple adders are too slow for n > 16.| FF Type | Excitation Table (Q→Q⁺) | Characteristic Eq. | Symbol |
|---|---|---|---|
| SR (Set-Reset) | 00→Q, 01→1, 10→0, 11→X | Q⁺ = S + R̄·Q | Forbidden: S=R=1 |
| JK | 00→Q, 01→0, 10→1, 11→Q̄ | Q⁺ = JQ̄ + K̄Q | Toggle on J=K=1 |
| D (Data) | 0→0, 1→1 | Q⁺ = D | Simplest, 1 input |
| T (Toggle) | 0→Q, 1→Q̄ | Q⁺ = T⊕Q = TQ̄ + T̄Q | Toggle when T=1 |
| From → To | Input Equations |
|---|---|
| SR → JK | S = JQ̄, R = KQ |
| SR → D | S = D, R = D̄ |
| SR → T | S = TQ̄, R = TQ |
| JK → D | J = D, K = D̄ |
| JK → T | J = T, K = T |
| JK → SR | J = S, K = R (with S·R=0 constraint) |
| D → JK | D = JQ̄ + K̄Q |
| D → T | D = T⊕Q |
| Type | Behavior | Symbol |
|---|---|---|
| Level-Triggered | Output changes while clock = HIGH (or LOW) | Triangle at clock input |
| Positive Edge | Output changes on LOW→HIGH transition of clock | Triangle + rising edge arrow |
| Negative Edge | Output changes on HIGH→LOW transition of clock | Triangle + falling edge bubble |
| Master-Slave JK | Master loads on HIGH, slave updates on LOW | Pulse-triggered; avoids 1s catching |
┌─────────────────────────────────────────────────────────────────┐
│ SEQUENTIAL CIRCUIT DESIGN PROCEDURE │
├─────────────────────────────────────────────────────────────────┤
│ │
│ STEP 1: State Diagram / State Table │
│ • Define states, inputs, outputs │
│ • Draw transitions for each input combination │
│ │
│ STEP 2: State Assignment │
│ • Assign binary codes to states (binary, Gray, one-hot) │
│ • One-hot: n states → n flip-flops (simpler, more FFs) │
│ • Binary: log₂(n) flip-flops (compact, more logic) │
│ │
│ STEP 3: Excitation Table │
│ • For chosen FF type, determine inputs needed for each │
│ present state → next state transition │
│ │
│ STEP 4: K-Map Simplification │
│ • Create K-map for each FF input and each output │
│ • Simplify expressions │
│ │
│ STEP 5: Circuit Implementation │
│ • Draw logic diagram using simplified expressions │
│ │
│ EXAMPLE: Design Mod-3 Up Counter using T-FFs │
│ States: 00 → 01 → 10 → 00 (3 states) │
│ Present | Next | T₁ | T₀ │
│ 00 | 01 | 0 | 1 │
│ 01 | 10 | 1 | 1 │
│ 10 | 00 | 1 | 0 │
│ 11 | XX | X | X (don't care) │
│ │
│ K-map T₁: T₁ = Q₁ + Q₀ │
│ K-map T₀: T₀ = Q̄₁ │
│ │
│ MEALY vs MOORE: │
│ Moore: Output depends ONLY on present state │
│ • Output changes on clock edge only │
│ • One state delay │
│ Mealy: Output depends on present state AND inputs │
│ • Output can change asynchronously with inputs │
│ • Faster response, but potential glitches │
└─────────────────────────────────────────────────────────────────┘Q⁺ = JQ̄ + K̄Q covers all cases. For one-hot state encoding, each state gets its own flip-flop — this simplifies the next-state logic dramatically and is preferred in FPGA designs.| Counter | FF Count | Mod | Freq at MSB |
|---|---|---|---|
| 3-bit Ripple Up | 3 | 8 | f_clk / 8 |
| 4-bit Ripple Up | 4 | 16 | f_clk / 16 |
| n-bit Ripple Up | n | 2ⁿ | f_clk / 2ⁿ |
| Mod-N (N < 2ⁿ) | n | N | Clear at count = N |
| Ripple Down | n | 2ⁿ | Complement output drives clock |
| Counter | Type | T-FF Equations |
|---|---|---|
| Mod-16 Up | 4-bit binary | T₀=1, T₁=Q₀, T₂=Q₀Q₁, T₃=Q₀Q₁Q₂ |
| Mod-16 Down | 4-bit binary | T₀=1, T₁=Q̄₀, T₂=Q̄₀Q̄₁, T₃=Q̄₀Q̄₁Q̄₂ |
| Mod-10 (BCD) | 4-bit decimal | Count 0-9, clear at 10 (1010) |
| Ring | Shift register | D₀ = Qₙ₋₁ (circular shift) |
| Johnson (Twisted Ring) | Shift register | D₀ = Q̄ₙ₋₁; Mod = 2n |
┌─────────────────────────────────────────────────────────────────┐
│ COUNTER DESIGN — KEY FORMULAS │
├─────────────────────────────────────────────────────────────────┤
│ │
│ MODULO COUNTER: │
│ Mod = Number of unique states │
│ Mod-N counter counts 0 to N-1, then resets │
│ FF count = ⌈log₂(N)⌉ │
│ │
│ SYNCHRONOUS UP COUNTER DESIGN (Mod-N using JK-FF): │
│ 1. Determine # of FFs: n = ⌈log₂(N)⌉ │
│ 2. Write count sequence (0 to N-1) │
│ 3. Find toggle conditions from state transitions │
│ 4. For JK: J=K=1 when that bit toggles (0→1 or 1→0) │
│ │
│ CASCADING COUNTERS: │
│ To build Mod-M × Mod-N = Mod-MN counter: │
│ • Ripple cascade: MSB output → clock of next counter │
│ • Synchronous cascade: TC output → ENT of next counter │
│ • Overall mod = product of individual mods (if coprime) │
│ │
│ RING COUNTER: │
│ n FFs, only ONE is HIGH at any time │
│ Mod = n (e.g., 4-bit ring → Mod-4) │
│ Advantage: No decoding glitches; self-decoding │
│ Disadvantage: Uses more FFs for same mod │
│ │
│ JOHNSON (TWISTED RING) COUNTER: │
│ n FFs, Mod = 2n │
│ D₀ = Q̄ₙ₋₁ (complemented feedback) │
│ Always has 50% duty cycle on every output │
│ Decoding: only 2-input AND gates needed (adjacent bits) │
│ │
│ STATE DIAGRAM COUNTER DESIGN (arbitrary sequence): │
│ Use present-state/next-state table │
│ Map to FF excitation tables │
│ Simplify with K-maps → combinational logic │
└─────────────────────────────────────────────────────────────────┘74LS161/163 (4-bit synchronous counter) and 74LS191/193 (up/down) are standard ICs. For arbitrary sequences, use the state-table approach with K-maps for each FF input.| Type | Volatile? | Read/Write | Speed | Use Case |
|---|---|---|---|---|
| SRAM | Yes | R/W | Fastest (1–10 ns) | Cache memory |
| DRAM | Yes | R/W | Fast (10–100 ns) | Main memory |
| ROM | No | R only | Fast | Boot firmware, lookup tables |
| PROM | No | R only (program once) | Fast | Low-volume production |
| EPROM | No | R only (UV erase) | Fast | Prototyping |
| EEPROM | No | R/W (byte-level) | Moderate | Config data |
| Flash | No | R/W (block-level) | Fast read, slow write | USB drives, SSDs |
| Feature | SRAM | DRAM |
|---|---|---|
| Storage Cell | 6 transistors (flip-flop) | 1 transistor + 1 capacitor |
| Refresh | Not needed | Required every ~64 ms (row refresh) |
| Density | Lower | Higher (4–8× SRAM) |
| Power | Higher (always active) | Lower (refresh only) |
| Cost | More expensive | Cheaper per bit |
| Access Time | ~1–10 ns | ~10–100 ns |
| Package | L2/L3 cache | Main memory (DDR4/DDR5) |
┌─────────────────────────────────────────────────────────────────┐
│ MEMORY ORGANIZATION & ADDRESSING │
├─────────────────────────────────────────────────────────────────┤
│ │
│ MEMORY SIZE NOTATION: │
│ n address lines → 2ⁿ locations │
│ m data lines → m bits per location │
│ Total bits = 2ⁿ × m │
│ │
│ Examples: │
│ 16K × 8 RAM: 14 address lines (2¹⁴ = 16384), 8 data lines │
│ 64K × 4 DRAM: 16 address lines, 4 data lines │
│ 1M × 16 ROM: 20 address lines, 16 data lines │
│ │
│ MEMORY EXPANSION: │
│ Word Expansion (increase data width): │
│ • Connect chips in parallel (same address bus) │
│ • Each chip provides subset of data bits │
│ • Example: Two 64K × 4 chips → 64K × 8 │
│ │
│ Address Expansion (increase locations): │
│ • Use decoder to select chip based on address bits │
│ • Example: Two 64K × 8 chips → 128K × 8 │
│ • Use higher address bits for chip selection │
│ │
│ Combined Expansion: │
│ • Use both techniques together │
│ • Four 64K × 4 chips → 128K × 8 memory │
│ • 2×2 arrangement (2 for word, 2 for address) │
│ │
│ DRAM REFRESH: │
│ • Each row must be read/written within refresh interval │
│ • 2¹⁰ rows refreshed every 64 ms │
│ • Refresh cycle: 64ms / 1024 = 62.5 µs per row │
│ • Methods: RAS-only refresh, CAS-before-RAS, Hidden refresh │
└─────────────────────────────────────────────────────────────────┘DDR (Double Data Rate) SDRAM which transfers data on both clock edges. For memory expansion, word expansion is parallel connection (same address), while address expansion uses a decoder to select between banks.| Type | Circuit | Resolution | Notes |
|---|---|---|---|
| Weighted Resistor | R, 2R, 4R, 8R... per bit | n bits | Simple but impractical for n > 4 (wide R range) |
| R-2R Ladder | Only R and 2R values | n bits | Most popular; easy to match resistors |
| Current Steering | Switched current sources | n bits | Fast; used in high-speed DACs |
| Type | Speed | Resolution | How It Works |
|---|---|---|---|
| Flash (Parallel) | Fastest (ns) | Up to 10-bit | 2ⁿ-1 comparators simultaneously; expensive |
| Successive Approx. | Medium (µs) | 8–16 bit | Binary search; 1 comparison per bit; best trade-off |
| Dual Slope | Slow (ms) | 12–20 bit | Integrate input, then reference; excellent noise rejection |
| Sigma-Delta (ΔΣ) | Variable | 16–24 bit | Oversampling + noise shaping; audio quality |
| Tracking | Variable | n bit | Up/down counter; follows slow changes |
┌─────────────────────────────────────────────────────────────────┐
│ ADC/DAC — KEY SPECIFICATIONS │
├─────────────────────────────────────────────────────────────────┤
│ │
│ RESOLUTION: │
│ # of bits (n) → 2ⁿ levels │
│ 8-bit: 256 levels | 12-bit: 4096 | 16-bit: 65536 │
│ Step size (V_LSB) = V_ref / 2ⁿ │
│ │
│ QUANTIZATION ERROR: │
│ Max = ±½ LSB = ±V_ref / (2 × 2ⁿ) │
│ % error = (1/2ⁿ) × 100% │
│ 8-bit: 0.39% | 12-bit: 0.024% | 16-bit: 0.0015% │
│ │
│ CONVERSION TIME: │
│ DAC: ~0 (instantaneous, limited by settling time) │
│ Flash ADC: ~tens of ns │
│ SAR ADC: n × T_clock (e.g., 12-bit @ 1MHz clk = 12 µs) │
│ Dual slope: fixed integration time + de-integration │
│ │
│ SUCCESSIVE APPROXIMATION REGISTER (SAR) ADC: │
│ Start: MSB = 1, rest = 0 │
│ If DAC output > V_in: MSB = 0 (too high) │
│ Else: MSB = 1 (keep it) │
│ Repeat for each bit MSB → LSB │
│ n bits require n clock cycles │
│ │
│ R-2R LADDER DAC: │
│ V_ref ─┬─[2R]─┬─[2R]─┬─[2R]─┬─[2R]─┐ │
│ │ │ │ │ │ │
│ [2R] [2R] [2R] [2R] [R_f]─┤→ V_out │
│ │ │ │ │ │ (inverting amp) │
│ └─[R]──┴─[R]──┴─[R]──┴─[R]──┘ │
│ GND S₃ S₂ S₁ S₀ │
│ Each switch: connected to V_ref (bit=1) or GND (bit=0) │
│ Output: V_out = -V_ref(R_f/R) × Σ(Dᵢ × 2⁻⁽ⁱ⁺¹⁾) │
└─────────────────────────────────────────────────────────────────┘Sigma-Delta ADCs provide 16–24 bit resolution with excellent linearity through oversampling and noise shaping.// ═══════════════════════════════════════════════════════
// VERILOG — BASIC MODULE STRUCTURE
// ═══════════════════════════════════════════════════════
module half_adder (
input A, B,
output Sum, Carry
);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule
// Full Adder using two half adders
module full_adder (
input A, B, Cin,
output Sum, Cout
);
wire w1, w2, w3;
assign w1 = A ^ B;
assign Sum = w1 ^ Cin;
assign w2 = A & B;
assign w3 = w1 & Cin;
assign Cout = w2 | w3;
endmodule
// D Flip-Flop with async reset
module d_ff (
input clk, rst, D,
output reg Q
);
always @(posedge clk or posedge rst) begin
if (rst)
Q <= 1'b0;
else
Q <= D;
end
endmodule// ═══════════════════════════════════════════════════════
// VERILOG — COUNTERS & STATE MACHINES
// ═══════════════════════════════════════════════════════
// 4-bit Up Counter with synchronous reset
module counter_4bit (
input clk, rst, en,
output reg [3:0] count
);
always @(posedge clk) begin
if (rst)
count <= 4'b0000;
else if (en)
count <= count + 1;
end
endmodule
// Moore State Machine (Sequence Detector: detects "1011")
module seq_detector_1011 (
input clk, rst, din,
output reg detected
);
// States: S0=idle, S1=got1, S2=got10, S3=got101, S4=got1011
reg [2:0] state, next_state;
always @(posedge clk or posedge rst) begin
if (rst) state <= 3'b000;
else state <= next_state;
end
always @(*) begin
next_state = state; // default
detected = 1'b0;
case (state)
3'b000: begin // S0: idle
if (din) next_state = 3'b001;
end
3'b001: begin // S1: got "1"
if (!din) next_state = 3'b010;
end
3'b010: begin // S2: got "10"
if (din) next_state = 3'b011;
end
3'b011: begin // S3: got "101"
if (din) begin
next_state = 3'b100;
detected = 1'b1;
end else next_state = 3'b010;
end
3'b100: begin // S4: got "1011"
if (din) next_state = 3'b001;
else next_state = 3'b010;
end
endcase
end
endmodule| Type | Usage | Example |
|---|---|---|
| wire | Combinational signal | wire [7:0] data; |
| reg | Procedural assignment (inside always) | reg [3:0] counter; |
| integer | Loop variable (32-bit) | integer i; |
| parameter | Constant | parameter WIDTH = 8; |
| input | Module input port | input clk; |
| output | Module output port | output reg [7:0] q; |
| Operator | Type | Description |
|---|---|---|
| & | ^ ~ | Bitwise | AND, OR, XOR, NOT |
| && || ! | Logical | AND, OR, NOT (0/1 result) |
| << >> | Shift | Left shift, right shift |
| === !== | Case | Equality with X/Z consideration |
| { , } | Concatenation | {a, b, 2'b00} → 6-bit |
| ?: | Conditional | mux: sel ? a : b |
wire and reg. A wire is driven by assign (continuous assignment, combinational). A reg is assigned inside always blocks (procedural). Note: reg does NOT necessarily imply a flip-flop — it depends on the sensitivity list.always @(posedge clk) infers flip-flops; always @(*) infers combinational logic.